Application Specific Integrated Circuits (ASICs) often have an internally generated clock, such as divide-down clock 102 shown in FIG. 1, that activates the internal logic of the ASIC. Internally generated clocks are generated from an external functional clock, e.g., functional clock 104. Frequently, the frequency of the functional clock is reduced using a frequency divider, e.g., frequency divider 106, which divides the frequency by x, where x is a numerical value greater than one. The division is performed to accommodate specific internal clock requirements.
In many instances, ASICs are tested for faults, such as stuck-at faults, e.g., stuck flip-flops. Flip-flops generate a stable one or zero signal depending on inputs. If flip-flops are stuck, problems occur with signal generation. Although there are multiple methods for design for testability (DFT), one of the most popular methods to test for stuck-at faults is scan insertion. Basically, flip-flops in the ASIC are replaced with scan flip-flops. These scan flip-flops have a multiplexer in front of the flip-flop that allows a selection between normal functional data or specially generated test patterns. The selector to the multiplexer is a scan enable signal that determines which data goes to the input of the flip-flop.
One problem when inserting scan flip-flops is how to control the clocks that drive the flip-flops. A popular method is to add a multiplexer, e.g., multiplexer 108, to the ASIC clock circuitry. An input pin of a multiplexer 108 is connected to an output of frequency divider 106, and another input pin of multiplexer 108 is connected to a test clock, e.g., test clock 110 shown in FIG. 1. A scan-insertion test signal, e.g., scan-tester 110, is connected to a select pin of multiplexer 108. Scan-tester 112 switches the ASIC between a functional mode and a test mode, selecting the functional clock for normal operation and the test clock for a testing operation. In functional mode, divide-down clock 102 (whose source is the output of frequency divider 106) drives the internal logic of the ASIC. In test mode, test clock 112 is now connected to divide-down clock 102 to drive the internal logic of the ASIC to test the operation of the ASIC.
Another problem associated with existing scan insertion ASIC testing is that the internally generated divide-down clock can be skewed relative to the functional clock, because the clocks are independent. Skewing is compounded between the functional clock and the internally generated divide-down clock because of the multiplexer added to control the scan flip-flops. The effect of the skew often causes timing issues that can lead to set-up and hold violations during testing.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for eliminating the skew between the functional clock and the internally generated divide-down clock used in existing scan insertion ASIC testing.